Former MIT Scientist’s Company Puts 64 Processors on a Chip

For two years, chipmaking biggies AMD and Intel have been locked in the Battle of the Multi-core Chips. First Intel pitted its Xeon and Core 2 chips against AMD’s dual-processor Athlon 64, and now both companies are doubling the stakes, with Intel releasing the Quad-Core Xeon and AMD about to bring out a four-processor chip code named Barcelona.

But there’s a Silicon Valley startup with operations in Westborough, MA, that’s leapfrogging both giants. It’s Tilera, which came out of stealth mode today to announce that it’s supplying a 64-processor chip called TILE64 to a dozen customers in the networking and digital multimedia processing sectors. The chip, based on technology developed by former MIT computer scientist Anant Agarwal, features an innovative mesh of switches that allows the 64 separate microprocessors on the chip to communicate with each other and with the outside world without the traffic jams of data that trouble multi-core integrated circuits with more classic designs.

“With the conventional architecture, if you try to double the number of cores, you run into some big problems—you have to significantly re-architect the main communications routes,” Tilera director of marketing Bob Doud told Xconomy in a call from the Hot Chips 19 symposium at Stanford University, where the company is making its public debut. “But with our mesh, as you add cores communications just takes care of itself. It’s like a city that grows at the edges.”

Multi-core chips are being used in a number of applications to handle several tasks simultaneously or to speed up the processing of large amounts of data. Intel and AMD’s consumer-level multi-core chips, for example, can handle multiple data-intensive jobs such as virus scanning and graphics rendering with less lag than single-processor chips. One problem with the multi-processor chips designed to date, however, is that the processors send data back and forth to one another and to external hardware via a central avenue or “bus,” an architecture originally developed for single-core chips. The bus becomes more and more saturated with data as additional processors are added, undermining the chips’ speed advantage.

Tilera says the processors on its TILE64 chip communicate via a two-dimensional grid of switches that the company calls “iMesh.” Like the grid layout in a city, the iMesh grid can soak up more traffic than a central avenue and provide a quicker path between any two processors. That, in turn, lowers power consumption. Tilera claims that the TILE64 runs commands 10 times faster than Intel’s dual-core Xeon, with 30 times the performance per watt of electricity consumed.

The combination of a core and a switch, in Tilera’s nomenclature, is a “tile” (hence the company’s name). Founder and chief technology officer Agarwal developed the tile architecture between 1997 and 2002 as part of the Raw Architecture Workstation (RAW) Project, an MIT effort funded by the Defense Advanced Research Projects Agency, the National Science Foundation, and the MIT AI Lab’s Project Oxygen. In 2004 Agarwal started Tilera, where it took several years to fine-tune the connecting mesh before a tile-based chip was ready for commercialization.

The TILE64 chips come with their own built-in management system called a “hypervisor” that’s capable of blocking off groups of tiles into islands, helping the chip to run multiple operating systems or applications or multiple instances of the same application. Customers can use the chip this way to get more performance out of existing applications. Or they can use Tilera’s own software development tool—the so-called “Multicore Development Environment,” which is based on an open-source development toolkit called Eclipse—to build new programs that divide a single data stream into multiple streams, processing them faster than conventional systems.

The company says this approach will be particularly useful for applications such as encrypting and decrypting high-definition TV signals or filtering Internet data for malicious viruses and worms. Doud says early Tilera customers include Top Layer Networks, a Westborough, MA, company that makes Internet intrusion detection equipment for corporate networks; Go Back TV, a Menlo Park, CA, company that provides a DVR-like ability to retrieve recorded video over cable networks; and Codian, a UK company that offers high-definition video conferencing services.

Tilera has venture funding from Bessemer Venture Partners, Columbia Capital, Walden International, and the VentureTech Alliance arm of Taiwan Semiconductor Manufacturing Company, which is also the company fabricating Tilera’s chips. It will likely face competition from Beaverton, OR-based Ambric and Sunnyvale, CA-based Stream Processors, which are also shipping multi-core chips with unconventional communications networks.

Wade Roush is a freelance science and technology journalist and the producer and host of the podcast Soonish. Follow @soonishpodcast

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